Regulations within the gaming industry have historically proscribed “writable” memory devices for the storage of computer codes that control the payoff aspects associated with a gaming machine. These code routines are so critical to operation that their corruption, either accidentally or deliberately, could result in cheating players. If such corruption occurred, even infrequently, it could pose a significant threat to the integrity of gaming operations. The storage of these codes is typically handled by a less volatile type of memory device, such as a read-only memory (ROM) or erasable programmable read-only memory (EPROM).
As the gaming industry moves toward game designs that utilize more multimedia style game presentation, the need for increased memory storage for game codes, graphics, sound, video, and the like grows dramatically. The use of EPROM style devices for data storage is becoming a significant burden and hindrance to the development of the gaming machines with enhanced capabilities. The use of cost effective, higher density mass storage devices is necessary.
In the personal computer industry, the need for large amounts of nonvolatile mass storage has not been nearly as significant. In fact, the opposite scenario is actually occurring. Current personal computer operating systems rely on the fact that data can be stored on the mass storage devices such as hard disks. This allows these operating systems to support virtual memory configurations, storage of recent web sites visited, storage of temporary recovery files in the event of a power interruption, and the like.
Gaming machines currently utilize parallel advanced technology attachment (PATA) IDE technology. The existing circuitry utilizes one of two techniques to protect the mass storage device from unauthorized commands. First, circuitry can electrically reside in the data stream between the PATA host and the mass storage device to intercept commands from the PATA host to the mass storage device. The PATA host characterizes the command as allowed or disallowed. The command is forwarded to the mass storage device if the command is allowed. Otherwise, the command is rejected and an invalid command is intentionally substituted and sent to the mass storage device. An error message is also sent to the PATA host to signal it of the fault condition.
Another technique provides for circuitry placed electrically adjacent to the data stream between the PATA host and mass storage device. The circuitry monitors each command from the host to the mass storage device. If a command is disallowed, an error bit is flagged in the control register and/or a non-maskable interrupt is set to the system. A hardwired reset line is also asserted to the mass storage device to prevent the disallowed operation from affecting the data content of the drive. Bypass of the mass storage protection system is also provided by manually installing a shorting jumper across a two pin header signaling the mass storage data protection device that all commands are now allowed.